The present disclosure relates to a display device preferable for an organic electroluminescence (EL) display device and a liquid crystal display device, and to an electronic apparatus including the display device.
In an active-drive liquid crystal display device or organic EL display device, a thin film transistor is used as a driving element, and a holding capacitance element holds electric charge corresponding to a signal voltage for writing a video image. If parasitic capacitance increases in a crossing region of a gate electrode of the thin film transistor and a source or drain electrode thereof, a variation in the signal voltage may occur, leading to degradation in image quality.
In particular, the organic EL display device needs to have a large holding capacitance for a large parasitic capacitance, leading to an increase in occupancy of wirings in a pixel layout. This results in an increase in probability of an inter-wiring short and the like, leading to a reduction in production yield.
In the past, attempts have been made to reduce the parasitic capacitance, which is formed in a crossing region of a gate electrode and a source or drain electrode, for thin film transistors including oxide semiconductor such as zinc oxide (ZnO) or indium-gallium-zinc oxide (IGZO) as channels.
For example, Japanese Unexamined Patent Application Publication No. 2007-220817 and J. Park et al., “Self-Aligned Top-Gate Amorphous Gallium Indium Zinc Oxide Thin Film Transistors”, Applied Physics Letters, American Institute of Physics, 2008, 93, 053501 describe a self-aligned top-gate thin film transistor, in which a gate electrode and a gate insulating film are formed in the same shape on a channel region of an oxide semiconductor thin-film layer, and then resistance of a region, which is not covered with the gate electrode and the gate insulating film, of the oxide semiconductor thin-film layer is decreased so that the region is formed into a source/drain region. R. Hayashi et al. “Improved Amorphous In—Ga—Zn—O TFTs”, SID 08 DIGEST, 2008, 42.1, pp. 621-624 describes a self-aligned bottom-gate thin film transistor, in which a source and drain regions are formed in an oxide semiconductor film through back exposure with a gate electrode as a mask.